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3.5.3.3
Offset Cancellation
The device provides an optional offset cancellation circuit to remove internal offset error. A block diagram of the offset cancel-
lation is shown in Figure 19 .
OFFSET CANCELLATION
INC/DEC
OUT
TO_OUTPUT SCALING
INPUT DATA
n + ( n ? z – 1 )
a ? -------------------------------------
d + ( d ? z – 1 )
LOW-PASS FILTER
1 2
0
1 2
Input Data downsampled to 256 μ s
0.5 Hz (Derived from f OS C )
OFFMON NEG
COUNTER
CLK
INC/DEC
OUT
UP/DOWN
OFF_ERR
OFFMON POS
2 kHz (Derived from f OSC )
COUNTER
CLK
OFFMON CNTLIMIT
do 1 + ( do 2 ? z – 1 )
Figure 19. Offset Cancellation Block Diagram
The transfer function for the offset LPF is:
no 1 + ( no 2 ? z – 1 )
H ( z ) = ao 0 ? ----------------------------------------------
Response parameters are specified in Section 2 and the offset LPF coefficients are specified in Table 6 .
During startup, two phases of the offset LPF are used to allow for fast convergence of the internal offset error during initializa-
tion. The timing and characteristics of each phase are shown in Table 5 and Table 6 and specified in Section 2 . For more infor-
mation regarding the startup timing, reference the PSI5 initialization information in Section 4.4 . The offset low-pass filter used in
normal operation is selected by the OC_FILT bit as shown in Table 5 .
During the Initialization Self-Test phase, the offset cancellation circuit output value is frozen.
During normal operation, output rate limiting is applied to the output of the high pass filter. Rate limiting updates the offset
cancellation output by OFF Step_xx LSB every t OffRate_xx seconds.
Table 5. Offset Cancellation Startup Characteristics and Timing
Offset Cancellation
Startup Phase
1
2
Self-Test
Complete
Offset LPF
10 Hz
0.3 Hz
0.3 Hz
0.1 Hz
Output Rate Limiting
Bypassed
Bypassed
Bypassed (Frozen during ST2)
Enabled
Total Time for Phase
80 ms
70 ms
96 ms per Self-Test Sequence (up to 6 repeats)
N/A
MMA52xxKW
Sensors
Freescale Semiconductor, Inc.
29
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